The present invention is related to testing of logic circuit designs, and in particular to the decompression of test results of logic testing and decompression of test results of the logic testing.
Testing of complex digital logic circuits requires the generation of a large number of test patterns. Unfortunately, the sizes of scan test patterns for today's large designs can be even larger than the sizes of a typical tester (i.e., an automated test equipment (ATE)) memory. This necessitates multiple loading of test patterns during a test application and, in turn, increases test application time and test cost. The oversized test pattern set problem is even more severe in delay testing, which has become a necessary test procedure for deep-sub micron chips. Delay test set sizes are often significantly larger than memory capacities of inexpensive testers. Test set sizes and test application times are major factors that determine the test cost of an integrated circuit.
One technique for addressing the issue is to compress the test data. Most prior art test data compression techniques proposed and developed for commercial use achieve compression by storing the seeds of a linear test pattern generator (e.g., such as a linear feedback shift register (LFSR) or a linear hybrid cellular automata (LHCA)) instead of the whole pattern.
The test pattern is generated from the seed by first loading the seed and then running the linear test pattern generator for several cycles. The seeds are obtained by solving a system of linear equations. Compression is achieved because many of the bits in the test patterns are, in fact, unspecified (“don't cares”). FIG. 1 shows the architecture of typical reseeding schemes, where a linear test pattern generator 104 is loaded with an m-bit seed by the tester and is then run in autonomous mode to produce a scan chain pattern to fill scan chain 108. The generator can be directly connected to the scan chain in the case of a single scan chain in the design or connected to multiple scan chains using a phase shifter 112.
In one LFSR reseeding scheme, the compression obtained is limited by the worst case scenario (i.e., the most specified scan test pattern). This is because, in order to be able to compress all the scan test patterns in the test set, the size of the LFSR is traditionally 20 more than the maximum number of specified bits Smax amongst all scan test patterns. However, most scan test patterns have much fewer specified bits than Smax, and a smaller seed will be enough to generate them. Hence, the efficiency is reduced by using the worst case seed size for the scan test patterns.
Compression schemes that are independent of an automatic test pattern generator (ATPG), usually based on coding theory, have the disadvantage that the design of the decompressor is dependent on the actual test patterns. Any changes in the test patterns (e.g., due to last minute design changes), will require the decompressor to be redesigned. On the other hand, compression schemes based on LFSR reseeding, though not fully independent of ATPG (i.e., not applicable with any scan test patterns), can be thought of as almost independent since typically the only requirement is on the Smax of the generated scan test patterns. Any ATPG can be used to generate the scan test patterns, and as long as the Smax of the patterns is less than a particular number, these schemes can be used to compress the scan test patterns without any loss in fault coverage.
For compression schemes that utilize only the unspecified bits in the scan test patterns, the maximum compression will still be limited by the total specified bits. For typical values of specified bits (e.g., 1% to 2%), the maximum compression that can be achieved is typically 50 times-100 times. To get higher compression, schemes that combine current techniques with another level of compression is required. Higher compression is often useful with the scaling of technology. In particular, more test patterns can be generated, and more fault models accommodated, especially to cover the new defects.
Therefore, there remains a need to more efficiently test logic circuit designs.